1. Field of the Invention
This invention relates to a semiconductor memory device.
2. Description of the Related Art
In recent years, transistors which configure SRAM cells are made smaller and the operation speed thereof is further enhanced as the capacity of the SRAM is increased and the operation speed thereof is further enhanced.
However, with a reduction in the size of the transistors, there occurs a problem that variation in the characteristics of the transistors configuring the SRAM cells becomes large and data of the SRAM cell is destroyed due to slight noises occurring in the SRAM cell. The main cause of generation of noises is that a leak current tends to occur due to the miniaturization of the transistors.
In order to solve the above problem, it is considered to use transistors having large channel width which are less influenced by noises. However, if the channel width of the transistor is increased, the area of the SRAM cell becomes larger and a reduction in the area of the transistors is prevented.
Therefore, a configuration having two transistors in addition to six transistors of the general configuration of an SRAM cell is proposed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-74965 [page 5, FIG. 2]). The SRAM cell has a bit line and word line for a write operation and a bit line and word line for a read operation instead of a word line and bit line of the conventional SRAM cell. By providing the write word line, read word line, write bit line and read bit line, even if transistors with small channel width are used, the SRAM cell can be less influenced. Further, since the transistor having small channel width can be used, the area of the SRAM cell can be reduced even though the number of transistors is increased by two.
However, with the recent requirement of further reducing the area of the SRAM cell, the above method of providing the word line and bit line for the write operation and the word line and bit line for the read operation delays the progress of reducing the area of the SRAM cell from the viewpoint of increasing the total number of word lines and bit lines. Thus, the above method cannot cope with a reduction in the area of the SRAM cell.